1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device by stacking a plurality of semiconductor chips, particularly to the CoW (Chip on Wafer) technology for obtaining semiconductor devices by stacking semiconductor chips on a semiconductor wafer.
2. Description of the Related Art
In a semiconductor device manufacturing process, a multiplicity of rectangular regions are demarcated by planned dividing lines formed in a grid pattern in the face-side surface of a circular disk-shaped semiconductor wafer, electronic circuits such as ICs and LSIs are formed at the surfaces of the rectangular regions, then the back side of the semiconductor wafer is ground, followed by polishing or the like if necessary, and thereafter the semiconductor wafer is cut and divided, or diced, along all the planned dividing lines, to obtain a multiplicity of semiconductor chips. The semiconductor chips thus obtained are packaged by sealing with a resin, and the packaged semiconductor chips are widely used in various electric and electronic apparatuses, such as cellular phones and PCs (personal computers).
Meanwhile, the demand in recent years for semiconductor devices higher in function and smaller in size has been increasing more and more. In relation to mounting technologies for meeting the demand, a semiconductor device configuration in which a plurality of semiconductor chips are stacked on and joined to one another has been put to practical use. Methods for manufacturing such a chip stack type semiconductor device include the one that is called CoW as above-mentioned. This is a method in which at least one semiconductor chip is stacked on each of the semiconductor chips of the semiconductor wafer yet to be diced into the multiplicity of semiconductor chips, and thereafter the wafer is cut along the planned dividing lines by use of a cutting blade or the like. As an electrode structure suited to the stacking of semiconductor chips, a technology relating to through-electrodes in which electrodes are formed in via holes formed in a wafer has been proposed by the present applicant (Japanese Patent Laid-open No. 2007-67082).
In the above-mentioned CoW, at the time of stacking the individual semiconductor chips one on each of the semiconductor chips of the wafer yet to be divided, each stacked-side semiconductor chip has to be accurately positioned in the area of each wafer-side semiconductor chip surrounded by the planned dividing lines, in such a manner as not to interfere with the planned dividing lines. If the wafer is divided along the planned dividing lines under the condition where the stacked-side semiconductor chip is interfering with the planned dividing line of the wafer by contacting or covering the planned dividing line, the stacked chip would be cut or sprung out, resulting in a defective product.
In addition, when the stack height is increased due to an increase in the number of semiconductor chips to be stacked on one another, the distance from the uppermost semiconductor chip in the stack to the wafer is enlarged, and, to cope with this, the amount of protrusion of the cutting edge of the cutting blade is increased. In such a case, usually, a cutting blade with a comparatively large thickness is used, so as to secure strength of the cutting blade. Where the comparatively thick cutting blade is used, each of the planned dividing lines is set to be comparatively large in width. This leads to a reduction in the number of semiconductor devices obtained per wafer, which is disadvantageous from the viewpoint of productivity.